US 12,093,694 B2
Device, method and system for provisioning a real branch instruction and a fake branch instruction to respective decoders
Mathew Lowes, Austin, TX (US); Jonathan Combs, Austin, TX (US); and Martin Licht, Round Rock, TX (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Mar. 26, 2021, as Appl. No. 17/214,693.
Prior Publication US 2022/0318020 A1, Oct. 6, 2022
Int. Cl. G06F 9/38 (2018.01)
CPC G06F 9/3844 (2013.01) [G06F 9/3804 (2013.01); G06F 9/3856 (2023.08)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit comprising:
first circuitry to determine that a branch predict table (BTB) is to provide a first entry which corresponds to a first instruction, wherein the first circuitry is to identify first address information which corresponds to the first instruction;
second circuitry, coupled to the first circuitry, to perform an evaluation, based on a classification of the first instruction as one of a fake branch instruction type, to detect whether the BTB includes another entry which corresponds both to the first address information, and to a respective instruction which is of the fake branch instruction type; and
third circuitry, coupled to the second circuitry, to provide a first double prediction eligibility state (DPES) parameter of the first entry based on the evaluation, wherein, for each entry of multiple entries of the BTB, a respective DPES parameter of the entry specifies a presence or an absence of a respective eligibility of a prediction, based on the instruction which corresponds to the entry, to be provided in a same fetch cycle with another prediction based on another instruction.