US 12,093,693 B2
Instruction set architecture for data processing array control
Xiao Teng, Cupertino, CA (US); Tejus Siddagangaiah, Santa Clara, CA (US); Bryan Lozano, San Jose, CA (US); Ehsan Ghasemi, San Jose, CA (US); Rajeev Patwari, San Jose, CA (US); Elliott Delaye, San Jose, CA (US); Jorn Tuyls, Leinster (IE); Aaron Ng, San Jose, CA (US); Sanket Pandit, San Jose, CA (US); Pramod Peethambaran, Los Gatos, CA (US); and Satyaprakash Pareek, Los Gatos, CA (US)
Assigned to Xilinx, Inc., San Jose, CA (US)
Filed by Xilinx, Inc., San Jose, CA (US)
Filed on Aug. 8, 2022, as Appl. No. 17/818,309.
Prior Publication US 2024/0045692 A1, Feb. 8, 2024
Int. Cl. G06F 9/30 (2018.01); G06F 9/38 (2018.01); G06F 9/46 (2006.01)
CPC G06F 9/3814 (2013.01) [G06F 9/3004 (2013.01); G06F 9/467 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method, comprising:
creating a replica of a register address space of a data processing array based on a design and the data processing array;
receiving a sequence of instructions including write instructions and read instructions, wherein the write instructions correspond to buffer descriptors specifying runtime data movements for a design for the data processing array;
converting the write instructions into transaction instructions and the read instructions into wait instructions based on the replica of the register address space;
including the transaction instructions and the wait instructions in an instruction buffer; and
performing at least one of providing the instruction buffer to a microcontroller configured to execute the transaction instructions and the wait instructions to implement the runtime data movements for the design as implemented in the data processing array or storing the instruction buffer to a file for subsequent execution by the microcontroller.