CPC G06F 9/30145 (2013.01) [G06F 9/30007 (2013.01); G06F 9/3001 (2013.01); G06F 9/30032 (2013.01); G06F 9/30043 (2013.01); G06F 9/30101 (2013.01); G06F 9/30105 (2013.01); G06F 9/3818 (2013.01); G06F 9/44505 (2013.01); G06F 12/0246 (2013.01); G06F 12/0292 (2013.01); G06F 16/322 (2019.01); G06F 16/41 (2019.01); G06F 16/9017 (2019.01); G11C 11/409 (2013.01); G06F 3/0647 (2013.01); G06F 9/30167 (2013.01); G06F 9/355 (2013.01); G06F 12/0811 (2013.01)] | 20 Claims |
1. A device comprising:
a memory configured to store a set of tables;
an intermediate register coupled to the memory;
a butterfly network coupled to the intermediate register;
a destination register coupled to the intermediate register;
a processor functional unit coupled to the memory; and
a decoder coupled to the processor functional unit and configured to:
receive an instruction that specifies a set of indices and the destination register;
based on the instruction, cause the processor functional unit to:
read a set of table elements from the set of tables by, for each table of the set of tables, reading a respective subset of the set of table elements based on a respective index of the set of indices; and
store the set of table elements in the intermediate register in a first order; and
based on the instruction, cause the butterfly network to:
reorder the set of table elements to be in a second order; and
store the set of table elements in the destination register in the second order.
|