US 12,093,688 B2
Multibit shift instruction
Michael Catherwood, Tyler, TX (US); David Mickey, Chandler, AZ (US); Ashish Desai, Chandler, AZ (US); Jason Sachs, Chandler, AZ (US); and Calum Wilkie, Chandler, AZ (US)
Assigned to Microchip Technology Incorporated, Chandler, AZ (US)
Filed by Microchip Technology Incorporated, Chandler, AZ (US)
Filed on Nov. 17, 2022, as Appl. No. 17/989,067.
Application 17/989,067 is a continuation of application No. 17/982,980, filed on Nov. 8, 2022, abandoned.
Claims priority of provisional application 63/285,752, filed on Dec. 3, 2021.
Prior Publication US 2023/0176867 A1, Jun. 8, 2023
Int. Cl. G06F 9/30 (2018.01)
CPC G06F 9/30032 (2013.01) [G06F 9/30123 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An article of manufacture comprising a non-transitory machine-readable medium, the medium comprising instructions, the instructions, when read and executed by a processor, cause the processor to execute a shift instruction, the shift instruction to cause a source data in memory to be shifted left or shifted right, the source data including a plurality of source words, the shift instruction to include a source parameter to identify the source data, the shift instruction to include a bit size parameter to identify a specified number of bits by which the source data is to be shifted, through:
a shift of a first source word of the source data by the specified number of bits to yield a first intermediate word;
a shift of a second source word of the source data by the specified number of bits to yield a second intermediate word and a first set of shifted-out bits; and
execution of a logical OR operation on the first intermediate word and the first set of shifted-out bits to yield a first result word.