US 12,093,623 B2
Relocatable FPGA modules
Michael Riepe, San Jose, CA (US); Kamal Choundhary, Santa Clara, CA (US); Amit Singh, San Jose, CA (US); Shirish Jawale, San Jose, CA (US); Karl Koehler, Freemont, CA (US); Simon Longcroft, London (GB); Scott Senst, Walker, MN (US); Clark Hilbert, San Jose, CA (US); and Kent Orthner, Santa Cruz, CA (US)
Assigned to Achronix Semiconductor Corporation, Santa Clara, CA (US)
Filed by Achronix Semiconductor Corporation, Santa Clara, CA (US)
Filed on Jul. 25, 2023, as Appl. No. 18/226,108.
Application 18/226,108 is a continuation of application No. 17/532,599, filed on Nov. 22, 2021, granted, now 11,853,669.
Prior Publication US 2023/0367940 A1, Nov. 16, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 30/30 (2020.01); G06F 15/78 (2006.01); G06F 30/31 (2020.01); G06F 30/347 (2020.01); G06F 30/392 (2020.01)
CPC G06F 30/347 (2020.01) [G06F 30/31 (2020.01); G06F 30/392 (2020.01); G06F 15/7825 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method comprising:
accessing, by one or more processors, a design for a programmable integrated circuit comprising a plurality of clusters disposed on a plurality of cluster rows and a plurality of cluster columns, each cluster comprising programmable logic and a network on chip (NoC) endpoint;
accessing, by the one or more processors, a selection of a selected portion of the design, that is within a cluster of the plurality of clusters and located at a determined offset from the NoC endpoint of the cluster;
determining, by the one or more processors, a plurality of locations within the plurality of clusters that the selected portion of the design can be relocated to without recompilation based on the determined offset; and
causing to be presented, by the one or more processors, a user interface that indicates the selected portion of the design and at least a subset of the determined plurality of locations.