US 12,093,619 B2
Automated circuit generation
Calum MacRae, Charlotte, NC (US); John Mason, Sunnyvale, CA (US); and Karen Mason, Sunnyvale, CA (US)
Assigned to Celera, Inc., San Jose, CA (US)
Filed by Celera, Inc., San Jose, CA (US)
Filed on May 8, 2023, as Appl. No. 18/314,029.
Application 18/314,029 is a continuation of application No. 17/507,504, filed on Oct. 21, 2021, granted, now 11,694,007.
Application 17/507,504 is a continuation of application No. 16/886,544, filed on May 28, 2020, granted, now 11,361,134.
Application 16/886,544 is a continuation of application No. 16/882,217, filed on May 22, 2020.
Claims priority of provisional application 62/854,848, filed on May 30, 2019.
Prior Publication US 2023/0274059 A1, Aug. 31, 2023
Int. Cl. G06F 30/327 (2020.01); G06F 30/31 (2020.01); G06F 30/347 (2020.01); G06F 30/367 (2020.01); G06F 30/373 (2020.01); G06F 30/38 (2020.01); G06F 30/392 (2020.01); G06F 30/398 (2020.01); G06F 111/12 (2020.01)
CPC G06F 30/327 (2020.01) [G06F 30/31 (2020.01); G06F 30/347 (2020.01); G06F 30/367 (2020.01); G06F 30/38 (2020.01); G06F 30/392 (2020.01); G06F 30/398 (2020.01); G06F 30/373 (2020.01); G06F 2111/12 (2020.01)] 46 Claims
OG exemplary drawing
 
1. A computer-implemented method of generating a transistor comprising:
receiving information specifying a transistor to be generated, said information comprising an on resistance of the transistor to be generated;
determining a total width of a gate of the transistor to be generated based at least on the on resistance;
determining a first width, a number of fingers (F), and a number of device cells (P) based on the total width;
generating a transistor level schematic comprising one or more transistors configured with the first width and the number of fingers (F); and
generating a layout, wherein the layout comprises P device cells, each device cell comprising a plurality of gates corresponding to said number of fingers (F), each gate having said first width, wherein the device cells are configured in a two-dimensional array.