US 12,093,569 B2
Memory device, host device and method of operating the memory device
Joo Hwan Kim, Seoul (KR); Su Cheol Lee, Suwon-si (KR); Jin Do Byun, Suwon-si (KR); Eun Seok Shin, Seoul (KR); Young Don Choi, Seoul (KR); and Jung Hwan Choi, Hwaseong-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Jul. 6, 2022, as Appl. No. 17/810,929.
Claims priority of application No. 10-2021-0150385 (KR), filed on Nov. 4, 2021.
Prior Publication US 2023/0138845 A1, May 4, 2023
Int. Cl. G11C 7/10 (2006.01); G06F 3/06 (2006.01); G11C 11/4096 (2006.01)
CPC G06F 3/0659 (2013.01) [G06F 3/061 (2013.01); G06F 3/0673 (2013.01); G11C 7/1057 (2013.01); G11C 7/1066 (2013.01); G11C 7/1084 (2013.01); G11C 7/1093 (2013.01); G11C 11/4096 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A memory device, comprising:
a data signal generator configured to generate a data signal;
a transmission driver configured to receive the data signal and output a multi-level signal having any one of a first signal level, a second signal level, and a third signal level based on the data signal;
a command decoder configured to receive a feedback signal from outside of the memory device and decode the feedback signal;
a data signal controller configured to adjust the data signal based on a decoding result of the command decoder; and
a drive strength controller configured to adjust at least one of the first to third signal levels based on the decoding result of the command decoder,
wherein the data signal is one of a first data signal and a second data signal,
the transmission driver comprises a pull-up circuit that receives the first data signal and a pull-down circuit that receives the second data signal, and
the drive strength controller adjusts at least one of the first to third signal levels by adjusting an on-resistance of the pull-up circuit and the pull-down circuit.