| CPC G06F 3/0659 (2013.01) [G06F 3/0611 (2013.01); G06F 3/0679 (2013.01); G06N 7/01 (2023.01); H03M 13/1575 (2013.01); H03M 13/616 (2013.01)] | 15 Claims |
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1. A memory system comprising:
a memory controller in communication with a host;
a memory device in communication with the memory controller;
a plurality of queues in the memory controller for holding respective subsets of a plurality of commands with different priorities;
a scheduler in the memory controller configured to schedule the plurality of commands for processing based on respective priorities and expected completion times of the commands for each of the plurality of commands with the different priorities in the queues; and
an error correction decoder in the memory controller operably coupled to the plurality of queues in the memory controller for receiving and decoding the commands according to respective schedules of the commands in the queues waiting for the error correction decoder, as determined by the scheduler,
wherein
in a first queue of the plurality of queues in the memory controller, a first set of commands of the plurality of commands are processed according to que-specific priorities of the first queue and que-specific expected completion times for the memory device to complete the first set of commands including execution latency of the error correction decoder,
the que-specific completion times of the commands in the first queue are based on predicted execution times for the memory device to execute the first set of commands,
predicted wait times for the first set of commands to wait in the first queue are considered by the scheduler,
between queuing the first set of commands in the first queue and sending the first set of commands to the error correction decoder, the scheduler determines an updated priority of a command in the first queue based a current priority, a predicted execution time, and a predicted wait time of the command, and
at each update cycle, the command with highest updated priority is sent to the error correction decoder,
wherein the memory system determines the expected completion times by estimating the execution latency of the error correction decoder, and
wherein the memory system estimates the execution latency of the error correction decoder based on syndrome weight.
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