US 12,093,543 B2
Memory training using electronic noise
Adam Shobash, Kfar Kama (IL)
Assigned to Amazon Technologies, Inc., Seattle, WA (US)
Filed by Amazon Technologies, Inc., Seattle, WA (US)
Filed on May 4, 2023, as Appl. No. 18/143,553.
Application 18/143,553 is a continuation of application No. 16/433,629, filed on Jun. 6, 2019, granted, now 11,709,604.
Prior Publication US 2023/0273735 A1, Aug. 31, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 3/06 (2006.01); G11C 11/4076 (2006.01)
CPC G06F 3/0632 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0659 (2013.01); G06F 3/0673 (2013.01); G11C 11/4076 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A system for computer memory training, the system comprising:
a memory attached to a circuit board;
a memory controller;
one or more ground lines between a ground of the memory controller and a ground of the circuit board; and
a connection between the memory controller and a transistor attached to the circuit board,
wherein the transistor is configured to activate or deactivate one or more of the ground lines responsive to a signal sent by the memory controller via the connection, and
wherein the memory controller is configured to:
increase an electronic noise level of the memory during a training phase by transmitting a signal to the transistor, via the connection, to deactivate one or more of the ground lines; and
perform a read centering operation for the memory while the electronic noise level is increased.