| CPC G06F 3/0631 (2013.01) [G06F 3/0611 (2013.01); G06F 3/0659 (2013.01); G06F 3/0679 (2013.01)] | 20 Claims |
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1. An apparatus, comprising:
processor circuitry configured to execute memory access operations for multiple traffic classes, including a first traffic class associated with a bandwidth quality-of-service parameter and a second traffic class;
memory controller circuitry configured to:
access storage circuitry to perform the memory access operations;
determine a temperature value associated with the storage circuitry;
based on detection of a first temperature scenario for the storage circuitry, allocate memory access operations among the first and second traffic class according to a first allocation policy, wherein the first allocation policy provides bandwidth to the first traffic class as a first multiple of bandwidth requested by an agent circuit for the first traffic class; and
in response to detection of a second temperature scenario for the storage circuitry, allocate memory access operations among the first and second traffic class according to a second allocation policy, wherein the second allocation policy provides bandwidth to the first traffic class as a second, greater multiple of bandwidth requested by the agent circuit for the first traffic class.
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