US 12,093,526 B2
Performance optimization device of memory system and operating method thereof
Ki Tae Kim, Gyeonggi-do (KR); Seon Ju Lee, Gyeonggi-do (KR); and In Ho Jung, Gyeonggi-do (KR)
Assigned to SK hynix Inc., Gyeonggi-do (KR)
Filed by SK hynix Inc., Gyeonggi-do (KR)
Filed on Apr. 21, 2022, as Appl. No. 17/725,684.
Claims priority of application No. 10-2021-0154794 (KR), filed on Nov. 11, 2021.
Prior Publication US 2023/0144376 A1, May 11, 2023
Int. Cl. G06F 3/06 (2006.01)
CPC G06F 3/0604 (2013.01) [G06F 3/0611 (2013.01); G06F 3/0655 (2013.01); G06F 3/0679 (2013.01)] 16 Claims
OG exemplary drawing
 
1. A method for operating a performance optimization device of a memory system, the method comprising:
determining N candidate performance parameter values for a performance parameter of the memory system, where N is a natural number greater than 0;
calculating N objective function results for an objective function defined for the memory system; and
determining an additional candidate performance parameter value for the performance parameter of the memory system, based on the N candidate performance parameter values and the N objective function results,
wherein each of the N objective function result is a result of the objective function, the result being measured when a corresponding one of the candidate performance parameter values is applied to the memory system, and
wherein the objective function is a function of an average of a plurality of latencies required for the memory system to process a plurality of commands received from an external device and a maximum value of the plurality of latencies,
wherein the average of a plurality of latencies is used to define throughput and the maximum value of the plurality of latencies is used to define delay time.