US 12,093,204 B2
SerDes interface circuit and control device
Kei Hagihara, Yamanashi (JP); and Tomomasa Nakama, Yamanashi (JP)
Assigned to Fanuc Corporation, Yamanashi (JP)
Appl. No. 17/793,723
Filed by Fanuc Corporation, Yamanashi (JP)
PCT Filed Feb. 16, 2021, PCT No. PCT/JP2021/005703
§ 371(c)(1), (2) Date Jul. 19, 2022,
PCT Pub. No. WO2021/166906, PCT Pub. Date Aug. 26, 2021.
Claims priority of application No. 2020-027946 (JP), filed on Feb. 21, 2020.
Prior Publication US 2023/0066398 A1, Mar. 2, 2023
Int. Cl. G06F 13/42 (2006.01)
CPC G06F 13/4282 (2013.01) [G06F 2213/0002 (2013.01)] 13 Claims
OG exemplary drawing
 
1. A control device for processing transmission data operating with a first clock of a first frequency, the control device comprising:
a SERializer/DESerializer (“SerDes”) configured to convert transmission parallel data into serial data of a predetermined communication rate by a second clock of a second frequency different form the first frequency;
a SerDes interface circuit configured to input the transmission data, convert and output Y-bit parallel data containing consecutive same data corresponding to the transmission data;
wherein the SerDes interface circuit comprises:
a First in First Out (“FIFO”) configured to input the first clock, the transmission data operating with the first clock and the second clock, and configured to output the transmission data by the second clock in an input order based on a control signal output from an output state machine;
a flip-flop configured to fetch and hold an output of the FIFO by the second clock; and
the output state machine being configured to input the output of the FIFO and an output of the flip-flop, and configured to generate parallel data containing consecutive bits of same logical value data corresponding to the transmission data by the second clock.