US 12,093,195 B2
Techniques for command bus training to a memory device
Christopher P. Mozak, Portland, OR (US); Steven T. Taylor, Beaverton, OR (US); and Alvin Shing Chye Goh, Bayan Lepas (MY)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Apr. 14, 2023, as Appl. No. 18/134,920.
Application 18/134,920 is a continuation of application No. 16/709,798, filed on Dec. 10, 2019, granted, now 11,675,716.
Prior Publication US 2023/0297523 A1, Sep. 21, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 12/00 (2006.01); G06F 9/30 (2018.01); G06F 13/16 (2006.01); G06F 13/42 (2006.01); G06F 18/214 (2023.01); G11C 7/10 (2006.01); G11C 7/22 (2006.01); H03M 13/09 (2006.01)
CPC G06F 13/1689 (2013.01) [G06F 9/30029 (2013.01); G06F 13/4243 (2013.01); G06F 18/214 (2023.01); G11C 7/1045 (2013.01); G11C 7/1048 (2013.01); G11C 7/222 (2013.01); H03M 13/09 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a controller logic configured to generate a first command to trigger a memory device to enter one of a first command bus training mode or a second command bus training mode to train a command and address (CA) interface of the memory device; and
input/output (I/O) circuitry configured to:
cause a CA pattern to be output via a command bus coupled with the CA interface of the memory device; and
receive a sampled CA pattern from the memory device via a data bus coupled with a DQ interface of the memory device, compress the sampled CA pattern to generate a first compressed value based on the memory device being in the first command bus training mode and forward the first compressed value to the controller logic; or
receive a second compressed value from the memory device via the data bus, the second compressed value to represent the sampled CA pattern compressed at the memory device based on the memory device being in the second command bus training mode and forward the second compressed value to the controller logic.