| CPC G06F 12/122 (2013.01) [G06F 2212/1016 (2013.01); G06F 2212/304 (2013.01)] | 1 Claim |
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1. An integrated circuit device, comprising:
memory access request intercept logic circuitry for memory management of a computing system, the memory access request intercept logic circuitry coupled between:
system level cache storing program data; and
a primary memory device and a secondary memory device that are external to the system level cache,
wherein the memory access request intercept logic circuitry is configured to:
periodically check counter values of counters implemented in a portion of the primary memory device, wherein the counters count transactions involving memory addresses in memory pages of the primary memory device;
determine, based on the counter values, that the memory pages were accessed less frequently than other memory pages of the primary memory device; and
select the memory pages for reallocation to the secondary memory device,
wherein the integrated circuit device further comprises a buffer configured to store updates to the counters, and
wherein the memory access request intercept logic circuitry is configured to buffer the updates to the counters and send one update to the counters for a total number of increments.
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