US 12,093,186 B2
Process dedicated in-memory translation lookaside buffers (TLBs) (mTLBs) for augmenting memory management unit (MMU) TLB for translating virtual addresses (VAs) to physical addresses (PAs) in a processor-based system
Madhavan Thirukkurungudi Venkataraman, Plano, TX (US); and Thomas Philip Speier, Wake Forest, NC (US)
Assigned to Microsoft Technology Licensing, LLC, Redmond, WA (US)
Filed by Microsoft Technology Licensing, LLC, Redmond, WA (US)
Filed on Sep. 27, 2023, as Appl. No. 18/373,792.
Application 18/373,792 is a division of application No. 17/582,556, filed on Jan. 24, 2022, granted, now 11,803,482.
Application 17/582,556 is a continuation of application No. 16/685,320, filed on Nov. 15, 2019, granted, now 11,232,042, issued on Jan. 25, 2022.
Prior Publication US 2024/0028522 A1, Jan. 25, 2024
Int. Cl. G06F 12/1027 (2016.01)
CPC G06F 12/1027 (2013.01) [G06F 2212/651 (2013.01); G06F 2212/681 (2013.01); G06F 2212/683 (2013.01)] 8 Claims
OG exemplary drawing
 
8. A method of dynamically resizing an allocation of a target in-memory TLB, comprising:
executing, in a central processing unit (CPU) in a processor comprising one or more CPUs, computer software instructions in an operating system software program or process;
storing, by a memory management system in the CPU, a physical address (PA), associated with a virtual address (VA), in one of a plurality of page table entries in one of a plurality of level page tables in a page table in a system memory, the page table entries each addressable by a different level index of the VA;
storing, in a memory management unit (MMU) translation lookaside buffer (TLB) entry of a plurality of MMU TLB entries, a cached page table entry of the plurality of page table entries;
storing, in an in-memory TLB entry of a plurality of in-memory TLB entries in an in-memory TLB in the system memory, a cached page table entry of the plurality of page table entries; accessing, by a page table walker circuit, a page table entry in the plurality of level page tables in the page table based on the VA;
storing, in each of a plurality of in-memory TLB address registers wherein each of the plurality of in-memory TLB address registers corresponds to a respective process of the one or more CPUs, a memory address pointing to a respective in-memory TLB, in the system memory, allocated to the respective process; and
dynamically resizing, in a CPU among the one or more CPUs, an allocation of a target in-memory TLB, in the system memory, comprising:
erasing the memory address, pointing to the target in-memory TLB, in one or more of the plurality of in-memory TLB address registers corresponding to the target in-memory TLB to be resized; and
issuing a cross call command to other CPUs among the one or more CPUs to cause the other CPUs to erase the memory address, pointing to the target in-memory TLB, in one or more of the plurality of in-memory TLB address registers corresponding to the target in-memory TLB to be resized.