US 12,093,184 B2
Processor-based system for allocating cache lines to a higher-level cache memory
Ramkumar Srinivasan, Saratoga, CA (US)
Assigned to QUALCOMM Incorporated, San Diego, CA (US)
Filed by QUALCOMM Incorporated, San Diego, CA (US)
Filed on Feb. 15, 2023, as Appl. No. 18/169,852.
Claims priority of provisional application 63/387,519, filed on Dec. 15, 2022.
Prior Publication US 2024/0202131 A1, Jun. 20, 2024
Int. Cl. G06F 12/08 (2016.01); G06F 12/0891 (2016.01); G06F 12/0897 (2016.01); G06F 12/12 (2016.01); G06F 12/126 (2016.01)
CPC G06F 12/0897 (2013.01) [G06F 12/0891 (2013.01); G06F 12/126 (2013.01)] 22 Claims
OG exemplary drawing
 
1. A processor-based system for allocating a cache line to a higher-level cache memory, comprising:
a lower-level cache memory configured to store data;
the processor-based system configured to, in response to an eviction request of a lower-level cache line in the lower-level cache memory:
determine whether the lower-level cache line is opportunistic;
set an opportunistic indicator to indicate whether the lower-level cache line is opportunistic;
communicate the lower-level cache line and the opportunistic indicator indicating that the lower-level cache line is opportunistic to the higher-level cache memory;
determine, based on the opportunistic indicator of the lower-level cache line, whether a higher-level cache line of a plurality of higher-level cache lines in the higher-level cache memory has less or equal importance than the lower-level cache line; and
in response to the determining the higher-level cache line has less or equal importance than the lower-level cache line:
replace the higher-level cache line in the higher-level cache memory with the lower-level cache line; and
associate the opportunistic indicator of the lower-level cache line in the higher-level cache memory.