US 12,093,182 B2
Typed store buffers for hardening store forwarding
Michael LeMay, Hillsboro, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Dec. 24, 2021, as Appl. No. 17/561,817.
Prior Publication US 2022/0114104 A1, Apr. 14, 2022
Int. Cl. G06F 12/0875 (2016.01); G06F 9/30 (2018.01); G06F 9/38 (2018.01); G06F 9/54 (2006.01); G06F 12/1027 (2016.01)
CPC G06F 12/0875 (2013.01) [G06F 9/30098 (2013.01); G06F 9/3826 (2013.01); G06F 9/3836 (2013.01); G06F 9/544 (2013.01); G06F 12/1027 (2013.01)] 17 Claims
OG exemplary drawing
 
1. An apparatus to store typed store buffers, the apparatus comprising:
processing circuitry to facilitate a store buffer to receive a portion of a store instruction, wherein the portion of the store instruction comprises a data operand and a first object capability register operand which comprises a first object type identifier for a first object, wherein the processing circuitry is to:
obtain, from a load instruction, a second object capability register operand which comprises a second object type identifier;
determine whether the first object type identifier matches the second object type identifier; and
block the portion of the store instruction from being loaded into the load instruction in response to a determination that the first object type identifier does not match the second object type identifier.