US 12,093,179 B2
Store-to-load forwarding correctness checks using physical address proxies stored in load queue entries
John G. Favor, San Francisco, CA (US); and Srivatsan Srinivasan, Cedar Park, TX (US)
Assigned to Ventana Micro Systems Inc., Cupertino, CA (US)
Filed by Ventana Micro Systems Inc., Cupertino, CA (US)
Filed on May 18, 2022, as Appl. No. 17/747,513.
Application 17/747,513 is a continuation in part of application No. 17/370,009, filed on Jul. 8, 2021, granted, now 11,481,332.
Application 17/747,513 is a continuation in part of application No. 17/351,946, filed on Jun. 18, 2021, granted, now 11,397,686.
Application 17/747,513 is a continuation in part of application No. 17/351,927, filed on Jun. 18, 2021, granted, now 11,416,406.
Application 17/370,009 is a continuation in part of application No. 17/351,927, filed on Jun. 18, 2021, granted, now 11,416,406.
Application 17/370,009 is a continuation in part of application No. 17/351,946, filed on Jun. 18, 2021, granted, now 11,397,686.
Application 17/351,927 is a continuation in part of application No. 17/315,262, filed on May 7, 2021, granted, now 11,416,400.
Application 17/370,009 is a continuation in part of application No. 17/315,262, filed on May 7, 2021, granted, now 11,416,400.
Application 17/351,946 is a continuation in part of application No. 17/315,262, filed on May 7, 2021, granted, now 11,416,400.
Application 17/747,513 is a continuation in part of application No. 17/315,262, filed on May 7, 2021, granted, now 11,416,400.
Claims priority of provisional application 63/331,487, filed on Apr. 15, 2022.
Claims priority of provisional application 63/271,934, filed on Oct. 26, 2021.
Prior Publication US 2022/0358044 A1, Nov. 10, 2022
Int. Cl. G06F 12/08 (2016.01); G06F 12/0864 (2016.01)
CPC G06F 12/0864 (2013.01) [G06F 2212/6032 (2013.04)] 21 Claims
OG exemplary drawing
 
1. A microprocessor, comprising:
a load/store unit configured to perform store-to-load forwarding;
a physically-indexed physically-tagged second-level set-associative cache, wherein each entry in the second-level cache is uniquely identified by a set index and a way of the second-level cache;
a store queue having store entries, wherein each store entry is configured to hold, for an associated store instruction to which the store entry has been allocated:
a store physical address proxy (PAP) for a store physical memory line address that is a translation of a store virtual memory line address specified by the associated store instruction, wherein the store PAP specifies the set index and the way of the entry in the second-level cache into which a cache line specified by the store physical memory line address is allocated; and
a load queue having load entries, wherein each load entry is configured to hold, for an associated load instruction to which the load entry has been allocated:
a load PAP for a load physical memory line address that is a translation of a load virtual memory line address specified by the associated load instruction, wherein the load PAP specifies the set index and the way of the entry in the second-level cache into which a cache line specified by the load physical memory line address is allocated; and
forwarding information about store-to-load forwarding with respect to the associated load instruction; and
wherein the load/store unit is configured to:
make a comparison of the store PAP associated with the store instruction with the load PAP of each valid entry of the load queue whose associated load instruction is younger in program order than the store instruction; and
use the comparison, along with the associated forwarding information, to make a store-to-load forwarding correctness check with respect to each younger load instruction.