US 12,093,176 B2
Memory circuit and cache circuit configuration
Hsien-Hsin Sean Lee, Duluth, GA (US); William Wu Shen, Hsinchu (TW); and Yun-Han Lee, Hsinchu County (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD, Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu (TW)
Filed on Jun. 26, 2023, as Appl. No. 18/341,088.
Application 15/248,093 is a division of application No. 13/667,924, filed on Nov. 2, 2012, granted, now 9,431,064, issued on Aug. 30, 2016.
Application 18/341,088 is a continuation of application No. 17/568,199, filed on Jan. 4, 2022, granted, now 11,687,454.
Application 17/568,199 is a continuation of application No. 16/587,215, filed on Sep. 30, 2019, granted, now 11,216,376, issued on Jan. 4, 2022.
Application 16/587,215 is a continuation of application No. 15/248,093, filed on Aug. 26, 2016, granted, now 10,430,334, issued on Oct. 1, 2019.
Prior Publication US 2023/0333981 A1, Oct. 19, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 12/0891 (2016.01); G06F 12/0804 (2016.01); G11C 5/02 (2006.01); G11C 5/04 (2006.01); G11C 7/22 (2006.01)
CPC G06F 12/0804 (2013.01) [G06F 12/0891 (2013.01); G11C 5/025 (2013.01); G11C 5/04 (2013.01); G11C 7/22 (2013.01); G06F 2212/1008 (2013.01); G06F 2212/1032 (2013.01); G06F 2212/45 (2013.01); G06F 2212/608 (2013.01); H01L 2224/16225 (2013.01); H01L 2924/15311 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory system, comprising:
multiple groups of primary memory cells residing in a first die or a stack of first dies;
multiple groups of cache memory cells residing in a second die, wherein each group of the cache memory cells is associated with a corresponding group of the primary memory cells, and wherein the first die or the stack of first dies is coupled to a top surface of the second die through a first group of bumps;
an interposer, wherein a bottom surface of the second die is coupled to a top surface of the interposer through a second group of bumps; and
control circuits residing in a third die, wherein the control circuits are associated with the primary memory cells and the cache memory cells, and wherein the third die is positioned aside the second die and coupled to the top surface of the interposer through a third group of pumps.