US 12,093,172 B2
Memory system and method of controlling nonvolatile memory
Shinichi Kanno, Ota (JP)
Assigned to KIOXIA CORPORATION, Tokyo (JP)
Filed by KIOXIA CORPORATION, Tokyo (JP)
Filed on Jun. 19, 2023, as Appl. No. 18/337,205.
Application 18/337,205 is a continuation of application No. 17/500,465, filed on Oct. 13, 2021, granted, now 11,720,487.
Application 17/500,465 is a continuation of application No. 16/815,894, filed on Mar. 11, 2020, granted, now 11,176,032, issued on Nov. 16, 2021.
Claims priority of application No. 2019-155834 (JP), filed on Aug. 28, 2019.
Prior Publication US 2023/0333980 A1, Oct. 19, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 13/16 (2006.01); G06F 12/02 (2006.01); G06F 12/1009 (2016.01); G11C 16/08 (2006.01); G11C 16/26 (2006.01)
CPC G06F 12/0246 (2013.01) [G06F 12/1009 (2013.01); G06F 13/1673 (2013.01); G11C 16/08 (2013.01); G11C 16/26 (2013.01); G06F 2212/7201 (2013.01)] 12 Claims
OG exemplary drawing
 
1. A memory system connectable to a host including a submission queue and a completion queue, the memory system comprising:
a nonvolatile memory including a plurality of blocks each including a plurality of pages; and
a controller configured to control the nonvolatile memory, wherein
the controller is configured to:
in response to receiving a first write command from the host through the submission queue of the host, determine a first physical address indicative of a physical storage location of the nonvolatile memory to which first write data associated with the first write command is to be written, and update an address translation table such that the first physical address is associated with a logical address of the first write data; and
transfer the first write data from a write buffer in a memory of the host to the controller, and write the first write data to a write destination location in a first write destination block of the nonvolatile memory, which is designated by the first physical address,
the controller is configured to start updating the address translation table before the transfer of the first write data is finished or before the write of the first write data to the nonvolatile memory is finished.