US 12,093,155 B2
Allocation of data sub-tensors onto hardware sub-arrays
Hee Jun Park, San Diego, CA (US); Bohuslav Rychlik, San Diego, CA (US); and Niraj Shantilal Paliwal, Nasik (IN)
Assigned to QUALCOMM Incorporated, San Diego, CA (US)
Filed by QUALCOMM Incorporated, San Diego, CA (US)
Filed on Sep. 24, 2021, as Appl. No. 17/448,864.
Prior Publication US 2023/0100036 A1, Mar. 30, 2023
Int. Cl. G06F 11/30 (2006.01); G06F 7/544 (2006.01); G06F 9/50 (2006.01); G06F 11/07 (2006.01); G06N 3/048 (2023.01)
CPC G06F 11/302 (2013.01) [G06F 7/5443 (2013.01); G06F 9/5066 (2013.01); G06F 11/0772 (2013.01); G06N 3/048 (2023.01)] 30 Claims
OG exemplary drawing
 
1. A method, comprising:
dividing an input data tensor into a first plurality of sub-tensors;
dividing a physical multiply-and-accumulate (MAC) array into a plurality of logical sub-arrays; and
for each respective sub-tensor of the first plurality of sub-tensors:
mapping the respective sub-tensor to a respective logical sub-array of the plurality of logical sub-arrays; and
processing the respective sub-tensor using the respective logical sub-array.