| CPC G05F 1/56 (2013.01) [H01L 23/5226 (2013.01); H01L 21/8238 (2013.01); H01L 27/092 (2013.01); H01L 29/417 (2013.01)] | 20 Claims |
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1. An integrated circuit device, comprising:
a plurality of rows of functional cells, each of the plurality of rows extending in a direction and having a cell height transverse to the direction in which the rows extend, at least one of the rows of functional cells comprising at least one digital low-dropout voltage regulator (DLVR) cell with the cell height for the row, the at least one DLVR cell comprising:
an input terminal;
a reference voltage terminal;
a voltage supply terminal;
an output terminal; and
a semiconductor layer comprising an active semiconductor region having a height smaller than the cell height;
one or more pairs of first and second transistors formed in the active semiconductor region, each pair arranged in cascode configuration connected between the voltage supply terminal and output terminal, each of the transistors having a gate, source and drain, the gate of the first one of transistor in each pair being connected to the voltage supply terminal connected to the input terminal, and the gate of the second transistor in each pair being connected to the reference voltage terminal,
wherein the input terminal, reference voltage terminal, voltage supply terminal and output terminal each comprises a respective one of a first, second, third, and fourth conductive lines formed in a layer of conductive lines disposed above the semiconductor layer, at least the third and fourth conductive lines are disposed directly above the active semiconductor region and spaced apart from each other by a distance of between about 10% and about 20% of the cell height.
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