US 12,092,958 B2
Wafer stage and method of using
Yung-Yao Lee, Hsinchu (TW); Wei Chih Lin, Hsinchu (TW); and Chih Chien Lin, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed on Jun. 3, 2022, as Appl. No. 17/832,297.
Application 17/832,297 is a division of application No. 17/083,868, filed on Oct. 29, 2020, granted, now 11,378,889.
Prior Publication US 2022/0291592 A1, Sep. 15, 2022
Int. Cl. G03F 7/00 (2006.01); H01L 21/027 (2006.01)
CPC G03F 7/70341 (2013.01) [G03F 7/70725 (2013.01); H01L 21/0274 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A wafer stage comprising:
an area for receiving a wafer;
a first sensor outside of the area for receiving the wafer;
a second sensor outside of the area of receiving the wafer, wherein the second sensor is spaced from the first sensor; and
a first particle capture area outside of the area for receiving the wafer, wherein the first particle capture area fails to overlap the area of receiving the wafer in a plan view, the first particle capture area is spaced from both the first sensor and the second sensor, a dimension of the first particle capture area in a first direction parallel to a top surface of the wafer stage is at least 26 millimeters (mm), a dimension of the first particle capture area in a second direction parallel to the top surface of the wafer stage is at least 33 mm, and the second direction is perpendicular to the first direction.