US 12,092,934 B2
Array substrate and display device
Hongfei Cheng, Beijing (CN); and Jianbo Xian, Beijing (CN)
Assigned to BOE TECHNOLOGY GROUP CO., LTD., Beijing (CN)
Filed by BOE TECHNOLOGY GROUP CO., LTD., Beijing (CN)
Filed on Aug. 18, 2022, as Appl. No. 17/890,451.
Application 17/890,451 is a continuation of application No. 15/521,303, granted, now 11,493,813, previously published as PCT/CN2016/101767, filed on Oct. 11, 2016.
Claims priority of application No. 201520876580.0 (CN), filed on Nov. 5, 2015.
Prior Publication US 2023/0017104 A1, Jan. 19, 2023
Int. Cl. H01L 27/12 (2006.01); G02B 30/27 (2020.01); G02F 1/13 (2006.01); G02F 1/1362 (2006.01); G02F 1/1368 (2006.01); G02F 1/136 (2006.01)
CPC G02F 1/136286 (2013.01) [G02B 30/27 (2020.01); G02F 1/13 (2013.01); G02F 1/136227 (2013.01); G02F 1/1368 (2013.01); H01L 27/1222 (2013.01); H01L 27/124 (2013.01); G02F 1/13606 (2021.01); G02F 2201/123 (2013.01)] 12 Claims
OG exemplary drawing
 
1. An array substrate comprising:
a base substrate;
a plurality of gate lines each extending in a first direction on the base substrate;
a plurality of data lines each extending in a second direction on the base substrate, the first direction intersecting with the second direction;
a pixel electrode arranged in a region enclosed by two adjacent gate lines of the plurality of gate lines and two adjacent data lines of the plurality of data lines; and
a thin film transistor arranged at an intersection between a gate line of the two adjacent gate lines and a data line of the two adjacent data lines, a drain of the thin film transistor being connected with the pixel electrode through a via hole,
wherein the gate line comprises a widening portion between the two adjacent data lines, the widening portion comprises a recess structure, and an orthogonal projection of the recess structure on the base substrate at least partly overlaps an orthogonal projection of the drain of the thin film transistor on the base substrate,
wherein the widening portion comprises a first widening portion and a second widening portion, both the first widening portion and the second widening portion are completely between the two adjacent data lines, and an orthographic projection of an active layer of the thin film transistor on the base substrate is within an orthographic projection of the first widening portion on the base substrate but does not overlap an orthographic projection of the second widening portion on the base substrate,
wherein orthographic projections of both a source and the drain of the thin film transistor on the base substrate at least partially overlap the orthographic projection of the first widening portion on the base substrate, but do not overlap the orthographic projection of the second widening portion on the base substrate, and
wherein the drain comprises a first segment, a second segment, and a third segment between and connecting the first segment and the second segment, an extension direction of the first segment is parallel with an extension direction of the data lines, an extension direction of the second segment is parallel with an extension direction of the gate lines, an orthogonal projection of the third segment on the base substrate at least partly overlaps the orthogonal projection of the recess structure on the base substrate to form an overlapping portion, the overlapping portion of the third segment comprises a straight portion, and an angle enclosed between an extension direction of a line connecting two ends of the straight portion and the extension direction of the gate lines is greater than 0° and smaller than 90°.