US 12,092,690 B2
Emulation of JTAG/SCAN test interface protocols using SPI communication device
Rakesh Kumar Polasa, Karnataka (IN); and Alagesan Mani, Tamil Nadu (IN)
Assigned to SILICONCH SYSTEMS PVT LTD, Karnataka (IN)
Filed by SILICONCH SYSTEMS PVT LTD, Karnataka (IN)
Filed on Apr. 28, 2023, as Appl. No. 18/140,930.
Claims priority of application No. 202241077541 (IN), filed on Dec. 31, 2022.
Prior Publication US 2024/0219464 A1, Jul. 4, 2024
Int. Cl. G01R 31/3183 (2006.01); G01R 31/3185 (2006.01)
CPC G01R 31/318314 (2013.01) [G01R 31/318536 (2013.01); G01R 31/318555 (2013.01)] 10 Claims
OG exemplary drawing
 
1. An apparatus for joint test action group (JTAG) and scan emulation, the apparatus comprising:
a controller circuitry that is interfaced to a target integrated circuit (IC) for testing the target IC, the controller circuitry having one or more serial peripheral interface (SPI) devices operating in master mode and slave mode, the one or more SPI devices having a plurality of pins to perform JTAG and scan emulation, the plurality of pins configured to:
emulate JTAG testing by using a clock (CLK) pin of a master SPI device to serve as a test clock (TCK) signal to a slave SPI device and the target IC;
provide a master output slave input (MOSI) pin of the master SPI device as a test data input (TDI) signal to the target IC;
provide a master input slave output (MISO) pin of the slave SPI device as a test mode select (TMS) signal for the target IC;
receive, from the target IC, a test data output (TDO) signal by the master input slave output (MISO) pin of the master SPI device; and
emulate scan testing by using the CLK pin of the master SPI device to serve as a serial clock (SCK) signal to the slave SPI device and the target IC;
provide the MOSI pin of the master SPI device and MISO pin of the slave SPI device as serial data input (SDI) signals to the target IC; and
receive, from the target IC, serial data output (SDO) signals by the MISO pin of the master SPI device and the MOSI pin of the slave SPI device, wherein the controller circuitry facilitates reusing the one or more SPI devices located in the controller circuitry to emulate JTAG and scan test interface protocols without any additional hardware requirements.