CPC G01R 31/3177 (2013.01) [G01R 31/2851 (2013.01); G01R 31/2884 (2013.01); G01R 31/31712 (2013.01); G01R 31/31713 (2013.01); G01R 31/31724 (2013.01); G01R 31/318572 (2013.01); G01R 31/3187 (2013.01); G11C 29/32 (2013.01); G11C 2029/5602 (2013.01)] | 20 Claims |
1. A single-wire bus circuit comprising:
a bus pin coupled to a single-wire bus;
a communication circuit coupled to the bus pin during a communication mode to carry out normal communications over the single-wire bus and decoupled from the bus pin during a test mode to undergo a test; and
a driver circuit coupled to the bus pin during the test mode and decoupled from the bus pin during the communication mode and comprising:
a plurality of test pins coupled to the communication circuit; and
a test driver circuit configured to operate in the test mode in each of a plurality of test cycles to:
provide one or more test input values to a first subset of the plurality of test pins to thereby cause the test to be performed in the communication circuit; and
receive one or more test output values resulting from the test performed in the communication circuit via a second subset of the plurality of test pins; and
a master circuit coupled to the bus pin via the single-wire bus and configured to communicate a test initiation command to the communication circuit during the communication mode to thereby instruct the communication circuit to switch from the communication mode to the test mode.
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