US 12,092,688 B2
Circuit for transferring data from one clock domain to another
Andreas Beermann, Stuttgart (DE); and Martin Mücke, Stuttgart (DE)
Assigned to Advantest Corporation, Tokyo (JP)
Filed by Advantest Corporation, Tokyo (JP)
Filed on Apr. 29, 2022, as Appl. No. 17/733,377.
Application 17/733,377 is a continuation of application No. PCT/EP2020/060143, filed on Apr. 9, 2020.
Prior Publication US 2022/0260635 A1, Aug. 18, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G01R 31/317 (2006.01); G01R 31/319 (2006.01); H03M 1/06 (2006.01); H03M 1/66 (2006.01); H04L 7/00 (2006.01)
CPC G01R 31/31727 (2013.01) [G01R 31/31726 (2013.01); G01R 31/31917 (2013.01); H03M 1/0624 (2013.01); H03M 1/66 (2013.01); H04L 7/0012 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A circuit for transferring a data from a first clock domain to a second clock domain, the circuit comprising:
a data synchronization circuit for generating a synchronized data signal;
a digital circuit associated with the second clock domain and coupled to the data synchronization circuit to receive the synchronized data signal, and wherein the digital circuit is configured to receive the synchronized data signal and to sample the synchronized data signal;
a phase comparator coupled to the digital circuit, wherein the phase comparator is configured to determine a phase relationship between a source clock signal of the first clock domain and a target clock signal; and
wherein the data signal synchronization circuit is coupled to the phase comparator and the digital circuit, wherein the data synchronization circuit is configured to receive a data signal synchronized to the source clock signal, and to provide the synchronized data signal to the digital circuit synchronized to the target clock signal, and
further the data signal synchronization circuit is configured to alternate operation between providing the synchronized data signal by sampling the data signal in response to a rising edge of the target clock signal and providing of the synchronized data signal by sampling the data signal in response to a falling edge of the target clock signal based on the phase relationship between the source clock signal and the target clock signal, and
wherein the source clock signal and the target clock signal have a predetermined frequency relationship.