US 12,092,685 B2
Chip and chip test system
Shu-Liang Ning, Hefei (CN)
Assigned to Changxin Memory Technologies, Inc., Hefei (CN)
Filed by Changxin Memory Technologies, Inc., Anhui (CN)
Filed on Mar. 24, 2021, as Appl. No. 17/211,366.
Application 17/211,366 is a continuation of application No. PCT/CN2019/106358, filed on Sep. 18, 2019.
Claims priority of application No. 201811137174.7 (CN), filed on Sep. 28, 2018; and application No. 201821631053.3 (CN), filed on Sep. 28, 2018.
Prior Publication US 2021/0208196 A1, Jul. 8, 2021
Int. Cl. G01R 31/28 (2006.01); G06F 30/333 (2020.01)
CPC G01R 31/2889 (2013.01) [G06F 30/333 (2020.01)] 18 Claims
OG exemplary drawing
 
1. A chip, coupled to a test equipment via a physical signal line and a data signal line, the chip comprising:
a decoding circuit, coupled to the physical signal line, and configured to decode a first input signal from the physical signal line and output a test mode signal or a test command signal, wherein the test mode signal is generated before the test command signal;
a test mode control circuit, coupled to the decoding circuit and the data signal line, and configured to set a test mode based on the test mode signal and a second input signal from the data signal line; and
a test command execution circuit, directly coupled to the decoding circuit, the test mode control circuit, and the data signal line, wherein the test command execution circuit is configured to respond to the test command signal based on the set test mode, and not to respond to the test command signal when no test mode is set.
 
11. A chip test system, comprising:
a test equipment, comprising a plurality of physical signal lines and a plurality of data signal lines, and configured to output a test signal after the output of a pre-activation signal to a chip under test; and
a plurality of chip test sites sharing the physical signal lines of the test equipment, wherein each of the plurality of chip test sites coupled to the test equipment via a respective data signal line and to a chip, wherein the chip comprises:
a decoding circuit, coupled to one of the physical signal lines, and configured to decode a first input signal from the one of the physical signal lines and output a test mode signal or a test command signal, wherein the test mode signal is generated before the test command signal;
a test mode control circuit, coupled to the decoding circuit and the data signal line, and configured to set a test mode based on the test mode signal and a second input signal from the data signal line; and
a test command execution circuit, directly coupled to the decoding circuit, the test mode control circuit, and the data signal line, wherein the test command execution circuit is configured to respond to the test command signal based on the set test mode, and not to respond to the test command signal when no test mode is set.