CPC G01R 19/0092 (2013.01) | 20 Claims |
1. An integrated circuit comprising:
a first circuit including a first amplifier, a first resistor, a second resistor, a third resistor, a fourth resistor, and a fifth resistor; wherein the first resistor has a first resistance (Rs); wherein the second resistor and the third resistor each have a second resistance (Rt); wherein the fourth resistor and the fifth resistor each have a third resistance (Rb); wherein the first resistor is configured to carry a first current (Isns) which is based on the first resistance (Rs) and a voltage differential between a first voltage (Vrect) and a second voltage (Vmid); wherein the first amplifier is configured to output a third voltage (Vo) based of the first current (Isns); wherein a gain of the first amplifier is based on the second resistance (Rt) and the third resistance (Rb);
wherein the first resistor is formed of a first plurality of polysilicon sheets; wherein the second resistor is formed of a second plurality of polysilicon sheets; wherein the third resistor is formed of a third plurality of polysilicon sheets; wherein the first plurality of polysilicon sheets, the second plurality of polysilicon sheets, and the third plurality of polysilicon sheets are disposed on a layer of the integrated circuit; wherein the second plurality of polysilicon sheets are arranged symmetrically to the third plurality of polysilicon sheets about an axis to reduce a stress differential between the second plurality of polysilicon sheets and the third plurality of polysilicon sheets.
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