US 12,419,157 B2
Double gate thin film transistor device with mixed semiconductor layers
Tae-Young Choi, Seoul (KR); Seung-Hwan Cho, Yongin-si (KR); and Byoungtaek Son, Seongnam-si (KR)
Assigned to Samsung Display Co., Ltd., Yongin-si (KR)
Filed by Samsung Display Co., Ltd., Yongin-si (KR)
Filed on Oct. 11, 2021, as Appl. No. 17/450,504.
Claims priority of application No. 10-2021-0015509 (KR), filed on Feb. 3, 2021.
Prior Publication US 2022/0246705 A1, Aug. 4, 2022
Int. Cl. H10K 59/121 (2023.01); H10D 30/67 (2025.01); H10D 86/40 (2025.01); H10D 86/60 (2025.01); H10H 29/10 (2025.01)
CPC H10K 59/1213 (2023.02) [H10D 30/6734 (2025.01); H10D 30/6743 (2025.01); H10D 30/6755 (2025.01); H10D 30/6757 (2025.01)] 22 Claims
OG exemplary drawing
 
1. A transistor comprising:
an active layer comprising:
a first end area comprising a first area containing boron ions, and a second area not doped with boron ions;
a middle area adjacent to the first area, and spaced from the second area by the first area; and
a second end area spaced from the first end area by the middle area;
a first electrode on the active layer, overlapping the second area, not overlapping the first area, and connected to the first end area through a first contact hole;
an upper gate electrode on the active layer, overlapping the middle area, at a same layer as the first electrode, and to receive a gate signal; and
a lower gate electrode under the active layer, overlapping the first contact hole and the middle area, and to receive the gate signal.