US 12,419,113 B2
Back-end-of-line semiconductor device structure providing a not-gate logic function and methods of forming the same
Yun-Feng Kao, New Taipei (TW); and Katherine H. Chiang, New Taipei (TW)
Assigned to Taiwan Semiconductor Manufacturing Company Limited, Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company Limited, Hsinchu (TW)
Filed on May 8, 2023, as Appl. No. 18/313,406.
Prior Publication US 2024/0379685 A1, Nov. 14, 2024
Int. Cl. H01L 27/12 (2006.01); H10D 86/01 (2025.01); H10D 86/40 (2025.01); H10D 86/60 (2025.01); H10D 87/00 (2025.01)
CPC H10D 87/00 (2025.01) [H10D 86/0221 (2025.01); H10D 86/423 (2025.01); H10D 86/60 (2025.01)] 20 Claims
OG exemplary drawing
 
14. A semiconductor device, comprising:
a substrate comprising a semiconductor material layer;
a plurality of device structures formed on or in the semiconductor material layer;
at least one interconnect-level dielectric layer over the substrate and the plurality of device structures and comprising conductive interconnect structures; and
a NOT gate logic circuit located over an interconnect-level dielectric layer, the NOT gate logic circuit comprising:
a first conductivity-type semiconductor layer;
a second conductivity-type semiconductor layer;
a first electrode contacting a first side surface of the first conductivity-type semiconductor layer;
a second electrode contacting a first side surface of the second conductivity-type semiconductor layer;
a dielectric isolation layer extending between the first conductivity-type semiconductor layer and the second conductivity-type semiconductor layer and between the first electrode and the second electrode;
a third electrode contacting a second side surface of the first conductivity-type semiconductor layer, a second side surface of the second conductivity-type semiconductor layer, and a side surface of the dielectric isolation layer;
a gate dielectric layer contacting the first conductivity-type semiconductor layer and the second conductivity-type semiconductor layer; and
a gate electrode contacting the gate dielectric layer.