US 12,419,109 B2
Array substrate and manufacturing method thereof, and display panel
Lizhong Wang, Beijing (CN); Guangcai Yuan, Beijing (CN); Ce Ning, Beijing (CN); Dongfang Wang, Beijing (CN); and Liping Lei, Beijing (CN)
Assigned to BOE TECHNOLOGY GROUP CO., LTD., Beijing (CN)
Appl. No. 18/278,413
Filed by BOE Technology Group Co., Ltd., Beijing (CN)
PCT Filed Sep. 26, 2022, PCT No. PCT/CN2022/121475
§ 371(c)(1), (2) Date Aug. 23, 2023,
PCT Pub. No. WO2024/065111, PCT Pub. Date Apr. 4, 2024.
Prior Publication US 2025/0015092 A1, Jan. 9, 2025
Int. Cl. H10D 86/60 (2025.01); G02F 1/1362 (2006.01); G02F 1/1368 (2006.01); H10D 86/40 (2025.01)
CPC H10D 86/60 (2025.01) [G02F 1/136209 (2013.01); G02F 1/136286 (2013.01); G02F 1/1368 (2013.01); H10D 86/441 (2025.01); H10D 86/421 (2025.01)] 20 Claims
OG exemplary drawing
 
1. An array substrate, comprising a display region and a non-display region located at a periphery of the display region, the array substrate comprising:
a substrate;
a first transistor and a second transistor that are disposed on the substrate, wherein the first transistor is disposed in the display region, and the second transistor is disposed in the non-display region; the first transistor comprises a first gate and a first active layer, the first gate being disposed on a side of the first active layer facing away from the substrate; and the second transistor comprises a second active layer and a second gate; and
a data line and a pixel electrode that are disposed in the display region, wherein the data line is disposed on a side of the first active layer close to the substrate and is lapped with the first active layer, and the pixel electrode is disposed on a side of the first gate facing away from the substrate and is lapped with the first active layer;
wherein the data line and the second gate are disposed in a same layer and made of a same material.