| CPC H10D 84/85 (2025.01) [H10D 30/014 (2025.01); H10D 30/43 (2025.01); H10D 30/6735 (2025.01); H10D 62/121 (2025.01); H10D 64/017 (2025.01); H10D 84/0167 (2025.01); H10D 84/038 (2025.01)] | 20 Claims |

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1. A semiconductor device, comprising:
a substrate comprising a nanosheet mesa
a stack of semiconductor nanosheets disposed on the nanosheet mesa;
a dielectric wall crossing through the nanosheet mesa and the stack of semiconductor nanosheets; and
a gate structure wrapping the stack of semiconductor nanosheets and crossing over the dielectric wall,
wherein a top of the dielectric wall has a recess.
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