US 12,419,100 B2
Transistor isolation regions and methods of forming the same
Szu-Ying Chen, Hsinchu (TW); Sen-Hong Syue, Zhubei (TW); Huicheng Chang, Tainan (TW); and Yee-Chia Yeo, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Jul. 31, 2023, as Appl. No. 18/362,707.
Application 18/362,707 is a division of application No. 17/385,561, filed on Jul. 26, 2021, granted, now 11,908,751.
Claims priority of provisional application 63/184,575, filed on May 5, 2021.
Prior Publication US 2023/0378000 A1, Nov. 23, 2023
Int. Cl. H10D 84/03 (2025.01); H01L 21/02 (2006.01); H01L 21/762 (2006.01); H10D 84/01 (2025.01); H10D 84/85 (2025.01)
CPC H10D 84/038 (2025.01) [H01L 21/0228 (2013.01); H01L 21/76224 (2013.01); H10D 84/0188 (2025.01); H10D 84/0193 (2025.01); H10D 84/853 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A device comprising:
a first semiconductor fin extending from a substrate;
a second semiconductor fin extending from the substrate;
a hybrid fin between the first semiconductor fin and the second semiconductor fin, the hybrid fin having a first curved bottom surface with a first arc length; and
an isolation region having a first portion, a second portion, and a third portion, the first portion disposed between the hybrid fin and the first semiconductor fin, the second portion disposed between the hybrid fin and the second semiconductor fin, the third portion disposed between the hybrid fin and the substrate, the isolation region having a second curved bottom surface with a second arc length, the second arc length less than the first arc length.