US 12,419,098 B2
Device integration schemes leveraging a bulk semiconductor substrate having a <111> crystal orientation
Mark Levy, Williston, VT (US); Jeonghyun Hwang, Ithaca, NY (US); and Siva P. Adusumilli, South Burlington, VT (US)
Assigned to GlobalFoundries U.S. Inc., Malta, NY (US)
Filed by GlobalFoundries U.S. Inc., Santa Clara, CA (US)
Filed on Mar. 14, 2024, as Appl. No. 18/604,627.
Application 18/604,627 is a division of application No. 17/890,446, filed on Aug. 18, 2022, granted, now 12,087,764.
Application 17/890,446 is a continuation of application No. 17/072,649, filed on Oct. 16, 2020, granted, now 11,469,225, issued on Oct. 11, 2022.
Prior Publication US 2024/0222366 A1, Jul. 4, 2024
Int. Cl. H10D 84/01 (2025.01); H10D 62/10 (2025.01); H10D 62/40 (2025.01); H10D 62/83 (2025.01); H10D 62/85 (2025.01); H10D 84/08 (2025.01); H10D 84/40 (2025.01)
CPC H10D 84/01 (2025.01) [H10D 62/115 (2025.01); H10D 62/405 (2025.01); H10D 62/83 (2025.01); H10D 62/8503 (2025.01); H10D 84/08 (2025.01); H10D 84/401 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A structure comprising:
a bulk semiconductor substrate comprising a single-crystal semiconductor material having a <111> crystal orientation, the bulk semiconductor substrate having a first device region, a second device region, and a trench;
a field-effect transistor including a source/drain region positioned in the single-crystal semiconductor material of the first device region of the bulk semiconductor substrate; and
a non-CMOS transistor in the second device region of the bulk semiconductor substrate, the non-CMOS transistor including a layer stack inside the trench on the single-crystal semiconductor material of the bulk semiconductor substrate, and the layer stack including a first layer comprising a first III-V compound semiconductor material.