| CPC H10D 64/671 (2025.01) [H01L 21/28123 (2013.01); H10D 30/024 (2025.01); H10D 30/6211 (2025.01); H10D 62/151 (2025.01)] | 20 Claims |

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1. A semiconductor device structure, comprising:
a substrate;
a gate stack disposed over the substrate;
a spacer structure disposed over a sidewall of the gate stack, wherein the spacer structure comprises a dielectric layer, a silicon rich layer, and a protection layer, wherein the dielectric layer is disposed between the gate stack and the silicon rich layer, wherein the silicon rich layer is disposed between the dielectric layer and the protection layer, wherein a first atomic percentage of silicon in the silicon rich layer is greater than about 50%; and
a source/drain structure disposed over the substrate, wherein the spacer structure is disposed between the source/drain structure and the gate stack, and wherein a portion of a side surface of the source/drain structure extends to a side surface of at least one of: the dielectric layer, the silicon rich layer, or the protection layer.
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