US 12,419,094 B2
Semiconductor device with trimmed channel region and method of making the same
Jia-Chuan You, Hsinchu (TW); Kuan-Ting Pan, Hsinchu (TW); Shi Ning Ju, Hsinchu (TW); Kuo-Cheng Chiang, Hsinchu (TW); and Chih-Hao Wang, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed on Aug. 5, 2021, as Appl. No. 17/395,071.
Prior Publication US 2023/0045491 A1, Feb. 9, 2023
Int. Cl. H10D 30/62 (2025.01); H10D 30/67 (2025.01); H10D 64/01 (2025.01); H10D 64/23 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01); H10D 84/83 (2025.01)
CPC H10D 64/258 (2025.01) [H10D 30/6735 (2025.01); H10D 30/6757 (2025.01); H10D 64/017 (2025.01); H10D 84/0151 (2025.01); H10D 84/038 (2025.01); H10D 84/83 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
an active area extending in a first direction over a substrate, the active area comprising a conductive path extending from a source region, through a channel region, to a drain region;
a gate dielectric on a surface of the channel region;
an isolating fin at a first side of the active area, wherein the isolating fin comprises
a first fin region having a first fin width adjacent to the source region,
a second fin region having a second fin width adjacent to the channel region, and
a third fin region having the first fin width adjacent to the drain region, wherein the first fin width is larger than the second fin width, and width is measured in a second direction perpendicular to the first direction; and
a gate electrode against the gate dielectric in the channel region.