US 12,419,093 B2
Structure of flash memory cell
Chih-Jung Chen, Hsinchu County (TW); and Yu-Jen Yeh, Taichung (TW)
Assigned to United Microelectronics Corp., Hsinchu (TW)
Filed by United Microelectronics Corp., Hsinchu (TW)
Filed on Nov. 8, 2023, as Appl. No. 18/504,165.
Application 18/504,165 is a division of application No. 17/855,700, filed on Jun. 30, 2022, granted, now 11,855,156.
Application 17/855,700 is a continuation of application No. 16/670,870, filed on Oct. 31, 2019, granted, now 11,417,734, issued on Aug. 16, 2022.
Prior Publication US 2024/0072129 A1, Feb. 29, 2024
Int. Cl. H01L 21/762 (2006.01); H10B 41/30 (2023.01); H10D 30/68 (2025.01); H10D 64/01 (2025.01); H10D 64/66 (2025.01); H01L 21/3105 (2006.01)
CPC H10D 64/035 (2025.01) [H01L 21/76224 (2013.01); H10B 41/30 (2023.02); H10D 30/68 (2025.01); H10D 64/015 (2025.01); H10D 64/679 (2025.01); H01L 21/31051 (2013.01)] 5 Claims
OG exemplary drawing
 
1. A structure of flash memory cell, comprising:
a substrate;
a floating gate, disposed on the substrate;
a low dielectric constant (low-K) spacer, disposed on a sidewall of the floating gate;
a trench isolation structure, having a base part disposed in the substrate and a protruding part above the substrate protruding from the base part; and
a tunnel oxide layer between the substrate and the floating gate,
wherein the low-K spacer is sandwiched between the floating gate and the protruding part of the trench isolation structure,
wherein a peripheral bottom flat surface of the floating gate directly covers on a portion of the base part of the trench isolation structure,
wherein the low-K spacer and the tunnel oxide layer are separated by a portion of the floating gate on the base part of the trench isolation structure,
wherein the low-K spacer comprises an air spacer, having a free space filled with air and a dielectric constant being close to 1,
wherein a dielectric constant of the low-K spacer is smaller than a dielectric constant of the trench isolation structure,
wherein a bottom surface of the tunnel oxide layer is lower than a bottommost surface of the low-K spacer.