US 12,419,091 B2
Source electrode and drain electrode protection for nanowire transistors
Karthik Jambunathan, Portland, OR (US); Biswajeet Guha, Hillsboro, OR (US); Anand S. Murthy, Portland, OR (US); and Tahir Ghani, Portland, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Jun. 29, 2022, as Appl. No. 17/853,320.
Application 17/853,320 is a continuation of application No. 16/646,124, granted, now 11,411,096, previously published as PCT/US2017/068624, filed on Dec. 28, 2017.
Prior Publication US 2022/0336634 A1, Oct. 20, 2022
Int. Cl. H10D 30/43 (2025.01); H10D 30/01 (2025.01); H10D 30/62 (2025.01); H10D 30/67 (2025.01); H10D 62/10 (2025.01); H10D 64/01 (2025.01); H10D 64/23 (2025.01); H01L 21/02 (2006.01); H10D 62/80 (2025.01); H10D 62/83 (2025.01); H10D 62/85 (2025.01); H10D 99/00 (2025.01)
CPC H10D 64/017 (2025.01) [H10D 30/014 (2025.01); H10D 30/43 (2025.01); H10D 30/6219 (2025.01); H10D 30/6713 (2025.01); H10D 30/6735 (2025.01); H10D 30/6757 (2025.01); H10D 62/121 (2025.01); H10D 64/018 (2025.01); H10D 64/251 (2025.01); H10D 64/258 (2025.01); H01L 21/02532 (2013.01); H01L 21/02535 (2013.01); H01L 21/02543 (2013.01); H01L 21/02546 (2013.01); H01L 21/02565 (2013.01); H01L 21/02603 (2013.01); H10D 30/021 (2025.01); H10D 30/031 (2025.01); H10D 30/6741 (2025.01); H10D 30/6743 (2025.01); H10D 30/675 (2025.01); H10D 30/6755 (2025.01); H10D 62/80 (2025.01); H10D 62/83 (2025.01); H10D 62/85 (2025.01); H10D 99/00 (2025.01)] 16 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a substrate;
a channel region including a nanowire above the substrate;
a metallic source electrode and a metallic drain electrode above the substrate, wherein the metallic source electrode is laterally separated from a first end of the nanowire by a first semiconductor layer between the metallic source electrode and the nanowire, the first semiconductor layer having an uppermost surface co-planar with an uppermost surface of the metallic source electrode, and the metallic drain electrode is laterally separated from a second end of the nanowire by a second semiconductor layer between the metallic drain electrode and the nanowire, the second semiconductor layer having an uppermost surface co-planar with an uppermost surface of the metallic drain electrode;
a gate electrode over and around the nanowire, the gate electrode having a lateral width between the metallic source electrode and the metallic drain electrode that is greater than a lateral width of the nanowire between the metallic source electrode and the metallic drain electrode;
a first spacer above the substrate between the gate electrode and the metallic source electrode, a second spacer above the substrate between the gate electrode and the metallic drain electrode; and
a gate dielectric layer between the channel region and the gate electrode.