US 12,419,085 B2
Integrated circuit structures having backside gate tie-down
Leonard P. Guler, Hillsboro, OR (US); Mauro J. Kobrinsky, Portland, OR (US); Mohit K. Haran, Hillsboro, OR (US); Marni Nabors, Portland, OR (US); Tahir Ghani, Portland, OR (US); Charles H. Wallace, Portland, OR (US); Allen B. Gardiner, Portland, OR (US); and Sukru Yemenicioglu, Portland, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Mar. 30, 2022, as Appl. No. 17/709,374.
Prior Publication US 2023/0317787 A1, Oct. 5, 2023
Int. Cl. H10D 62/10 (2025.01); H10D 84/83 (2025.01)
CPC H10D 62/121 (2025.01) [H10D 84/834 (2025.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit structure, comprising:
a first vertical stack of horizontal nanowires over a first sub-fin;
a second vertical stack of horizontal nanowires over a second sub-fin, the second vertical stack of horizontal nanowires spaced apart from and parallel with the first vertical stack of horizontal nanowires; and
a gate structure, comprising:
a first gate structure portion over the first vertical stack of horizontal nanowires, wherein the first gate structure extends along an entirety of the first sub-fin;
a second gate structure portion over the second vertical stack of horizontal nanowires, wherein the second gate structure does not extend along an entirety of the second sub-fin; and
a gate cut between the first gate structure portion and the second gate structure portion.