| CPC H10D 62/118 (2025.01) [H10D 30/031 (2025.01); H10D 30/6713 (2025.01); H10D 30/6735 (2025.01); H10D 30/6757 (2025.01); H10D 84/0128 (2025.01); H10D 84/013 (2025.01); H10D 84/0147 (2025.01); H10D 84/038 (2025.01); H10D 30/797 (2025.01)] | 20 Claims |

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1. A method comprising:
etching a source/drain recess in a nanostructure and a fin, a sidewall of the nanostructure exposed to the source/drain recess, a top surface of the fin exposed to the source/drain recess;
growing a first epitaxial layer and a second epitaxial layer in the source/drain recess, wherein the first epitaxial layer is grown on the sidewall of the nanostructure by exposing the sidewall of the nanostructure to a semiconductor-containing precursor, a blocker-containing precursor, and a dopant-containing precursor, wherein the second epitaxial layer is grown to cover an entirety of the top surface of the fin by exposing the top surface of the fin to the semiconductor-containing precursor, the blocker-containing precursor, and the dopant-containing precursor, wherein the second epitaxial layer is separated from the first epitaxial layer, wherein the second epitaxial layer is thicker than the first epitaxial layer;
growing a third epitaxial layer in the source/drain recess by exposing the first epitaxial layer and the second epitaxial layer to the semiconductor-containing precursor and the dopant-containing precursor, the first epitaxial layer and the second epitaxial layer not exposed to the blocker-containing precursor when growing the third epitaxial layer;
depositing a dielectric layer on the third epitaxial layer; and
forming a contact through the dielectric layer, the contact connected to the third epitaxial layer, the contact spaced apart from the first epitaxial layer.
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