| CPC H10D 30/475 (2025.01) [H10D 30/015 (2025.01); H10D 30/4755 (2025.01); H10D 62/824 (2025.01); H10D 62/8503 (2025.01)] | 20 Claims |

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1. An integrated chip, comprising:
an undoped layer overlying a substrate;
a first barrier layer overlying the undoped layer;
a doped layer overlying the first barrier layer; and
a second barrier layer overlying the first barrier layer, wherein the second barrier layer is laterally offset from a perimeter of the doped layer by a non-zero distance, wherein the first and second barrier layers comprise a same III-V semiconductor material, wherein a first atomic percentage of a first element within the first barrier layer is less than a second atomic percentage of the first element within the second barrier layer, wherein the first barrier layer comprises a first segment having a first thickness below the doped layer and a second segment having a second thickness directly adjacent to the first segment, wherein the second barrier layer has a third thickness, wherein the first thickness is greater than the second thickness and the third thickness, wherein the first segment has a top surface contacting a bottom surface of the doped layer and the second segment has a top surface contacting a bottom surface of the second barrier layer, wherein a bottom surface of the first segment is aligned with a bottom surface of the second segment, wherein the first segment contacts an inner sidewall of the second barrier layer.
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