| CPC H10D 30/024 (2025.01) [H10D 30/0243 (2025.01); H10D 30/6211 (2025.01); H10D 30/6735 (2025.01); H10D 30/6757 (2025.01); H10D 62/121 (2025.01); H10D 84/0135 (2025.01); H10D 84/014 (2025.01); H10D 84/0147 (2025.01); H10D 84/0151 (2025.01); H10D 84/0158 (2025.01); H10D 84/0172 (2025.01); H10D 84/038 (2025.01); H10D 84/0177 (2025.01); H10D 84/0188 (2025.01)] | 20 Claims |
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1. A device comprising:
a fin structure disposed on a substrate, the fin structure including a stack of semiconductor layers that are separated from each other;
a dielectric fin disposed on the substrate;
a spacer layer disposed on a sidewall of the dielectric fin and extending below the dielectric fin such that the spacer layer prevents the dielectric fin from interfacing with the substrate;
an interfacial layer wrapping around each semiconductor layer of the stack;
a gate dielectric layer disposed on the interfacial layer wrapping around each semiconductor layer of the stack, the gate dielectric layer extending to the spacer layer disposed on the sidewall of the dielectric fin; and
a gate electrode layer including a first portion wrapping around the gate dielectric layer disposed on the interfacial layer and a second portion extending along the spacer layer disposed on the sidewall of the dielectric fin, wherein an airgap extends between the first portion of the gate electrode layer and the second portion of the gate electrode layer,
wherein the fin structure includes a portion of the substrate having a top surface, and
wherein the airgap extends below the top surface of the portion of the substrate.
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9. A device comprising:
a substrate having a protrusion;
a first elongated semiconductor layer disposed over the protrusion;
a second elongated semiconductor layer disposed over the first elongated semiconductor layer, wherein the second elongated semiconductor layer is spaced apart from the first elongated semiconductor layer by a first distance measured in a first direction that is substantially perpendicular to a top surface of the substrate;
a dielectric fin disposed on the substrate, the dielectric fin having a first sidewall and an opposing second sidewall such that a bottom surface of the dielectric fin extends from the first sidewall to the second sidewall;
a spacer disposed directly on the first sidewall, the second sidewall and the bottom surface of the dielectric fin, wherein the spacer is separated from one of the first and second elongated semiconductor layers by a second distance, the second distance being measured in a second direction that is substantially parallel to the top surface of the substrate; and
a gate electrode layer including a first portion wrapping around the first and second elongated semiconductor layers and a second portion extending along a sidewall of the spacer, wherein an airgap extends between the first portion of the gate electrode layer and the second portion of the gate electrode layer,
wherein top surfaces of the spacer and the dielectric fin are coplanar.
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15. A device comprising,
a dielectric fin extending over a substrate;
a spacer disposed on a sidewall of the dielectric fin and extending below the dielectric fin such that the spacer prevents the dielectric fin from interfacing with the substrate;
a first channel layer disposed over the substrate and adjacent a first sidewall of the dielectric fin;
a second channel layer disposed over the first channel layer, wherein there is a first distance between the first channel layer and the second channel layer;
a third channel layer disposed over the substrate and adjacent an opposing second sidewall of the dielectric fin, wherein there is a second distance between the second sidewall of the dielectric fin and an end of the third channel layer;
a first metal layer disposed over the first channel layer, the second channel layer, and the third channel layer; and
a second metal layer disposed over the third channel layer.
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