US 12,419,072 B2
Transistor source/drain contacts and methods of forming the same
Pei-Wen Wu, Xinfeng Township (TW); Chun-Hsien Huang, Hsinchu (TW); Wei-Jung Lin, Hsinchu (TW); and Chih-Wei Chang, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Feb. 18, 2022, as Appl. No. 17/651,721.
Claims priority of provisional application 63/278,535, filed on Nov. 12, 2021.
Prior Publication US 2023/0155004 A1, May 18, 2023
Int. Cl. H10D 30/01 (2025.01); H10D 30/62 (2025.01); H10D 30/67 (2025.01); H10D 62/10 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01)
CPC H10D 30/024 (2025.01) [H10D 30/031 (2025.01); H10D 30/6211 (2025.01); H10D 30/6219 (2025.01); H10D 30/6713 (2025.01); H10D 30/6757 (2025.01); H10D 62/115 (2025.01); H10D 62/118 (2025.01); H10D 84/0128 (2025.01); H10D 84/013 (2025.01); H10D 84/0151 (2025.01); H10D 84/0158 (2025.01); H10D 84/038 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A method comprising:
depositing an inter-layer dielectric (ILD) over a source/drain region;
forming a contact opening through the ILD, wherein the contact opening exposes the source/drain region;
forming a metal-semiconductor alloy region on the source/drain region;
depositing a first layer of a conductive material on the metal-semiconductor alloy region, wherein the first layer of the conductive material extends over a top surface of the ILD;
after depositing the first layer of the conductive material, depositing an isolation material along inner sidewalls of the contact opening and over the first layer of the conductive material;
etching the isolation material to expose the first layer of the conductive material, wherein the isolation material extends along sidewalls of the contact opening after etching the isolation material; and
depositing a second layer of the conductive material on the first layer of the conductive material.