US 12,419,070 B2
Semiconductor device including III-V compound semiconductor layer and manufacturing method thereof
Da-Jun Lin, Kaohsiung (TW); Chih-Wei Chang, Tainan (TW); Fu-Yu Tsai, Tainan (TW); and Bin-Siang Tsai, Changhua County (TW)
Assigned to UNITED MICROELECTRONICS CORP., Hsin-Chu (TW)
Filed by UNITED MICROELECTRONICS CORP., Hsin-Chu (TW)
Filed on Jun. 6, 2022, as Appl. No. 17/833,885.
Claims priority of application No. 111116030 (TW), filed on Apr. 27, 2022.
Prior Publication US 2023/0352557 A1, Nov. 2, 2023
Int. Cl. H10D 30/01 (2025.01); H01L 21/265 (2006.01); H01L 23/31 (2006.01); H10D 30/47 (2025.01); H10D 62/824 (2025.01); H10D 62/85 (2025.01); H10D 64/01 (2025.01); H10D 64/27 (2025.01); H10D 64/62 (2025.01)
CPC H10D 30/015 (2025.01) [H01L 21/26546 (2013.01); H01L 23/3171 (2013.01); H10D 30/475 (2025.01); H10D 62/824 (2025.01); H10D 62/85 (2025.01); H10D 62/8503 (2025.01); H10D 64/01 (2025.01); H10D 64/411 (2025.01); H10D 64/62 (2025.01)] 5 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a III-V compound semiconductor layer;
a III-V compound barrier layer disposed on the III-V compound semiconductor layer;
a passivation layer disposed on the III-V compound barrier layer, wherein the passivation layer comprises:
a first region; and
a second region located above the first region, wherein a silicon concentration of the second region is higher than a silicon concentration of the first region;
a source doped region and a drain doped region disposed in the III-V compound semiconductor layer;
a source electrode and a drain electrode disposed on the source doped region and the drain doped region, respectively;
a source silicide layer disposed between the source electrode and the source doped region;
a drain silicide layer disposed between the drain electrode and the drain doped region, wherein the source silicide layer and the drain silicide layer are further disposed partly on the first region and the second region of the passivation layer;
a gate electrode disposed on the III-V compound semiconductor layer; and
a gate dielectric layer disposed between the gate electrode and the III-V compound semiconductor layer,
wherein the source silicide layer and the drain silicide layer are partly disposed on a top surface of the second region.