US 12,419,062 B2
Method for manufacturing semiconductor device including capacitor structure having lower electrode with different lengths
Wei-Jie Lin, Taichung (TW)
Assigned to NANYA TECHNOLOGY CORPORATION, New Taipei (TW)
Filed by NANYA TECHNOLOGY CORPORATION, New Taipei (TW)
Filed on Jul. 1, 2022, as Appl. No. 17/856,399.
Prior Publication US 2024/0006474 A1, Jan. 4, 2024
Int. Cl. H10D 1/00 (2025.01); H10D 1/68 (2025.01)
CPC H10D 1/043 (2025.01) [H10D 1/696 (2025.01); H10D 1/714 (2025.01); H10D 1/716 (2025.01)] 7 Claims
OG exemplary drawing
 
1. A method of manufacturing a semiconductor device, comprising:
providing a substrate including a central region and a peripheral region adjacent to the central region;
forming a lower sacrificial layer, a lower supporting layer, an upper sacrificial layer and an upper supporting layer on the substrate;
forming an through-hole defined by the lower sacrificial layer, the lower supporting layer, the upper sacrificial layer, and the upper supporting layer;
forming a conductive layer on the upper supporting layer and within the through-hole;
forming a cap layer over the conductive layer, wherein the cap layer defines an recess exposing the upper sacrificial layer;
removing the upper sacrificial layer to expose the lower supporting layer; and
performing an etching process to remove the lower supporting layer, wherein the peripheral region of the substrate is imposed on a first temperature, and the central region of the substrate is imposed on a second temperature different form the first temperature.