| CPC H10B 63/845 (2023.02) [G11C 5/063 (2013.01); H10B 63/30 (2023.02); H10N 70/231 (2023.02); H10N 70/021 (2023.02)] | 20 Claims |
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1. A cell array of a memory device, the cell array comprising:
a first deck of memory cells arranged in a first row and a second row extending in a first horizontal direction and a plurality of columns extending in a second horizontal direction perpendicular to the first horizontal direction, wherein the memory cells in the second row in the first deck is displaced in the first horizontal direction with respect to the memory cells in the first row in the first deck;
a first common word line metal track extending in the first horizontal direction, wherein both the memory cells in the first row in the first deck and the memory cells in the second row in the first deck are disposed on the first common word line metal track;
a plurality of first bit line metal tracks extending in the second horizontal direction, wherein each of the plurality of first bit line metal tracks is disposed on one of the first deck of memory cells;
a second deck of memory cells, wherein each of the second deck of memory cells is aligned with one of the first deck of memory cells in a vertical direction, and wherein each of the second deck of memory cells is disposed on one of the plurality of first bit line metal tracks;
a second common word line metal track extending in the first horizontal direction, wherein the second common word line metal track is disposed on both the memory cells in the first row in the second deck and the memory cells in the second row in the second deck;
a third deck of memory cells arranged in the first row and the second row extending in the first horizontal direction and the plurality of columns extending in the second horizontal direction, wherein each of the third deck of memory cells is aligned with one of the second deck of memory cells in the vertical direction;
a third common word line metal track extending in the first horizontal direction, wherein both the memory cells in the first row in the third deck and the memory cells in the second row in the third deck are disposed on the third common word line metal track;
a plurality of second bit line metal tracks extending in the second horizontal direction, wherein each of the plurality of second bit line metal tracks is disposed on one of the third deck of memory cells; and
a first vertical via extending in a vertical direction and connecting the first common word line metal track and the third common word line metal track.
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