US 12,419,042 B2
Integrated circuit device
Jiseok Hong, Suwon-si (KR); Sangho Lee, Seoul (KR); Seoryong Park, Ansan-si (KR); Jiyoung Ahn, Seoul (KR); Kiseok Lee, Seoul (KR); Kiseok Lee, Hwaseong-si (KR); Yoonyoung Choi, Seoul (KR); and Seunguk Han, Suwon-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Mar. 20, 2023, as Appl. No. 18/186,593.
Application 18/186,593 is a continuation of application No. 17/168,952, filed on Feb. 5, 2021, granted, now 11,647,627.
Claims priority of application No. 10-2022-0076763 (KR), filed on Jun. 23, 2020.
Prior Publication US 2023/0232616 A1, Jul. 20, 2023
Int. Cl. H10B 12/00 (2023.01)
CPC H10B 12/485 (2023.02) [H10B 12/0335 (2023.02); H10B 12/315 (2023.02); H10B 12/482 (2023.02)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit device, comprising:
a substrate comprising a plurality of active regions;
a device isolation layer on the substrate, the device isolation layer defining the plurality of active regions;
a plurality of bit lines spaced apart from each other on the substrate in a first direction, the plurality of bit lines extending in a second direction crossing the first direction, each of the plurality of bit lines comprising a metal layer, an uppermost surface of the metal layer of each of the plurality of bit lines being on a first level of a first line extending in the first line on the plurality of active regions and on the device isolation layer;
a direct contact provided between a first active region among the plurality of active regions and a first bit line among the plurality of bit lines;
an inner oxide layer contacting a sidewall of the direct contact; and
a carbon-containing oxide layer contacting a sidewall of the first bit line, the carbon-containing oxide layer being separate from the inner oxide layer.