| CPC H10B 10/125 (2023.02) [H10D 30/43 (2025.01); H10D 30/6729 (2025.01); H10D 30/6735 (2025.01); H10D 30/6757 (2025.01); H10D 62/121 (2025.01)] | 20 Claims |
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1. A memory structure, comprising:
a static random-access memory (SRAM) cell having a first pass-gate transistor and a second pass-gate transistor;
a word-line conductor extending in a first direction, wherein the word-line conductor is over and electrically connected to gate electrodes of the first pass-gate transistor and the second pass-gate transistor;
a first source/drain contact under and electrically connected to a source/drain feature of the first pass-gate transistor;
a second source/drain contact under and electrically connected to a source/drain feature of the second pass-gate transistor;
a bit-line conductor extending in a second direction perpendicular to the first direction, wherein the bit-line conductor is under and electrically connected to the first source/drain contact;
a bit-line-bar conductor extending in the second direction, wherein the bit-line-bar conductor is under and electrically connected to the second source/drain contact;
a first word-line landing pad extending in the second direction and over the first pass-gate transistor; and
a second word-line landing pad extending in the second direction and over the second pass-gate transistor,
wherein the word-line conductor is electrically connected to the gate electrodes of the first pass-gate transistor and the second pass-gate transistor respectively through the first word-line landing pad and the second word-line landing pad.
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