US 12,418,362 B1
Forward error correction in digital communication systems
Johan Adam Du Preez, Cape Town (ZA); and Frederick Jacobus Du Toit, Cape Town (ZA)
Assigned to Stellenbosch University, Stellenbosch (ZA)
Filed by STELLENBOSCH UNIVERSITY, Stellenbosch (ZA)
Filed on Jan. 29, 2025, as Appl. No. 19/040,282.
Claims priority of application No. 2405561 (GB), filed on Apr. 19, 2024.
Int. Cl. H03M 13/00 (2006.01); H04L 1/00 (2006.01)
CPC H04L 1/0061 (2013.01) 18 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a receiver for receiving a sequence of bits via a channel, the sequence of bits having been encoded at a source using a linear error correcting code; and
a decoder for decoding the received sequence of bits and outputting a decoded sequence of bits, wherein the decoder implements a message passing schedule determined using a cluster graph representation of the linear error correcting code for passing of joint distribution-based messages between parity check clusters of the cluster graph representation of the linear error correcting code, including iterating message passing until consensus between all the parity check clusters regarding shared bit values is reached, and outputting the decoded sequence of bits when consensus is reached.